MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 436

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.10.4 QADC64 Clock (QCLK) Generation
MPC555
USER’S MANUAL
The purpose of external gated continuous-scan mode is to continuously collect digi-
tized samples while the gate is open and to have the most recent samples available.
To ensure consistent sample times in waveform digitizing, for example, the program-
mer must ensure that all CCWs have identical sample time settings in IST.
It is up to the programmer to ensure that the queue is large enough so that a maximum
gate open time will not reach an end of queue. However it is useful to take advantage
of a smaller queue in the manner described in the next paragraph.
In the event that the queue completes before the gate closes, a completion flag will be
set and the queue will roll over to the beginning and continue conversions until the gate
closes. If the gate remains open and the queue completes a second time, the trigger
overrun flag will be set and the queue will roll-over again. The queue will continue to
execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops and QADC64 sets the PF1 bit to indicate an incomplete
queue. Software can read the CWPQ1 to determine the last valid conversion in the
queue. In this mode, if the gate opens again execution of queue 1 begins again. The
start of queue 1 is always the first CCW in the CCW table.
Interval Timer Continuous-Scan Mode. The QADC64 includes a dedicated periodic/
interval timer for initiating a scan sequence on queue 1 and/or queue 2. Software se-
lects a programmable timer interval ranging from 128 to 128 Kbytes times the QCLK
period in binary multiples. The QCLK period is prescaled down from the intermodule
bus (IMB) MCU clock.
When a periodic timer continuous-scan mode is selected for queue 1 and/or queue 2,
the timer begins counting. After the programmed interval elapses, the timer generated
trigger event starts the appropriate queue. Meanwhile, the QADC64 automatically per-
forms the conversions in the queue until an end-of-queue condition or a pause is en-
countered. When a pause occurs, the QADC64 waits for the periodic interval to expire
again, then continues with the queue. Once end-of-queue has been detected, the next
trigger event causes queue execution to begin again with the first CCW in the queue.
The periodic timer generates a trigger event whenever the time interval elapses. The
trigger event may cause the queue execution to continue following a pause or queue
completion, or may be considered a trigger overrun. As with all continuous-scan queue
operating modes, software action is not needed between trigger events.
Software enables the completion interrupt when using the periodic timer continuous-
scan mode. When the interrupt occurs, the software knows that the periodically col-
lected analog results have just been taken. The software can use the periodic interrupt
to obtain non-analog inputs as well, such as contact closures, as part of a periodic look
at all inputs.
Figure 13-8
for the A/D converter state machine, which controls the timing of the conversion. The
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
is a block diagram of the clock subsystem. The QCLK provides the timing
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
13-24