MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 294

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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8.12.3 Change of Lock Interrupt Register (COLIR)
U = Unaffected by reset
8.12.4 VDDSRAM Control Register (VSRMCR)
MPC555
USER’S MANUAL
COLIR — Change of Lock Interrupt Register
RESET:
MSB
Bit(s)
27:31
Bit(s)
10:15
0:7
0
0
26
10
8
9
The COLIR is 16-bit read/write register. It controls the change of lock interrupt gener-
ation, and is used for reporting a loss of lock interrupt source. It contains the interrupt
request level and the interrupt status bit. This register is readable and writable at any
time. A status bit is cleared by writing a one (writing a zero does not affect a status bit’s
value). The COLIR is memory mapped into the MPC555 / MPC556 USIU register map.
This register contains control bits for enabling or disabling the VDDSRAM supply de-
tection circuit. There are also four bits that indicate the failure detection. All four bits
have the same function and are required to improve the detection capability in extreme
cases.
/
1
0
MPC556
COLIRQ
COLIS
COLIE
Name
Name
DIVF
2
0
Table 8-10 PLPRCR Bit Descriptions (Continued)
3
0
COLIRQ
Reserved
The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be
read and written at any time. However, the DIVF field can be write-protected by setting the
MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL
to lose lock.
Change of lock interrupt request level. These bits determine the interrupt priority level of the
change of lock. To specify certain level, the appropriate one of these bits should be set.
If set (“one”), the bit indicates that a change in the PLL lock status was detected. The PLL
was locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared
by writing a one.
Reserved
Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will generate when the
COLIS bit is asserted.
0 = Change of lock Interrupt disable
1 = Change of lock Interrupt enable
Reserved
Freescale Semiconductor, Inc.
4
0
For More Information On This Product,
Table 8-11 COLIR Bit Descriptions
CLOCKS AND POWER CONTROL
5
0
Go to: www.freescale.com
Rev. 15 October 2000
6
0
7
0
COLIS
8
0
Description
Description
served
Re-
9
0
COLIE
10
U
11
U
12
U
Reserved
13
U
0x2F C28C
MOTOROLA
14
U
LSB
15
8-34
U

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