MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 419

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.5.3 Supervisor/Unrestricted Address Space
13.6 General-Purpose I/O Port Operation
MPC555
USER’S MANUAL
IMB3. The FRZ bit in QADC64MCR determines whether or not the QADC64 responds
to an IMB FREEZE assertion. Freeze mode is useful when debugging an application.
When the IMB FREEZE line is asserted and the FRZ bit is set, the QADC64 finishes
any conversion in progress and then freezes. Depending on when the FREEZE is as-
serted, there are three possible queue freeze scenarios:
When the QADC64 enters the freeze mode while a queue is active, the current CCW
location of the queue pointer is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer
is held in reset. External trigger events that occur during the freeze mode are not cap-
tured. The BIU remains active to allow IMB access to all QADC64 registers and RAM.
Although the QADC64 saves a pointer to the next CCW in the current queue, the soft-
ware can force the QADC64 to execute a different CCW by writing new queue operat-
ing modes for normal operation. The QADC64 looks at the queue operating modes,
the current queue pointer, and any pending trigger events to decide which CCW to ex-
ecute.
If the FRZ bit is clear, assertion of the IMB FREEZE line is ignored.
The QADC64 memory map is divided into two segments: supervisor-only data space
and assignable data space. Access to supervisor-only data space is permitted only
when the CPU is operating in supervisor mode. Assignable data space can have either
restricted to supervisor-only data space access or unrestricted supervisor and user
data space accesses. The SUPV bit in QADC64MCR designates the assignable
space as supervisor or unrestricted.
Attempts to read or write supervisor-only data space when the CPU is not in supervisor
mode cause the bus master to assert the internal transfer error acknowledge (TEA)
signal.
The supervisor-only data space segment contains the QADC64 global registers, which
include QADC64MCR, QADC64TEST, and QADC64INT. The supervisor/unrestricted
space designation for the CCW table, the result word table, and the remaining
QADC64 registers is programmable.
QADC64 port pins, when used as general-purpose input, are conditioned by a syn-
chronizer with an enable feature. The synchronizer is not enabled until the QADC64
decodes an IMB bus cycle which addresses the port data register to minimize the high-
• When a queue is not executing, the QADC64 freezes immediately
• When a queue is executing, the QADC64 completes the current conversion and
• If during the execution of the current conversion, the queue operating mode for
/
then freezes
the active queue is changed, or a queue 2 abort occurs, the QADC64 freezes im-
mediately
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
13-7