MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 156

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.11 Exception Model
3.11.1 Exception Classes
3.11.2 Ordered Exceptions
3.11.3 Unordered Exceptions
MPC555
USER’S MANUAL
For a memory access instruction, if the sum of the effective address and the operand
length exceeds the maximum effective address, the storage operand is considered to
wrap around from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit un-
signed binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
The PowerPC exception mechanism allows the processor to change to supervisor
state as a result of external signals, errors, or unusual conditions arising in the execu-
tion of instructions. When exceptions occur, information about the state of the proces-
sor is saved to certain registers, and the processor begins execution at an address
(exception vector) predetermined for each exception. Processing of exceptions occurs
in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the ex-
ception — for example, the DAE/source instruction service register (DSISR). Addition-
ally, some exception conditions can be explicitly enabled or disabled by software.
The MPC555 / MPC556 exception classes are shown in
In the MPC555 / MPC556, all exceptions except for reset, debug port non-maskable
interrupts, and machine check exceptions are ordered. Ordered exceptions satisfy the
following criteria:
Unordered exceptions may be reported at any time and are not guaranteed to pre-
serve program state information. The processor can never recover from a reset excep-
tion. It can recover from other unordered exceptions in most cases. However, if a
• Only one exception is reported at a time. If, for example, a single instruction en-
• When the exception is taken, no program state is lost.
/
counters multiple exception conditions, those conditions are encountered se-
quentially. After the exception handler handles an exception, instruction
execution continues until the next exception condition is encountered.
MPC556
Synchronous (ordered, precise)
Table 3-20 MPC555 / MPC556 Exception Classes
Asynchronous, unordered
Asynchronous, ordered
Freescale Semiconductor, Inc.
For More Information On This Product,
Class
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
Instruction-caused exceptions
External interrupt
Exception Type
Machine check
System reset
Decrementer
Table
3-20.
MOTOROLA
3-34