MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 700

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.2.1.2 History Buffer Flushes Status Pins— VFLS [0..1]
21.2.1.3 Queue Flush Information Special Case
21.2.2 Program Trace when in Debug Mode
MPC555
USER’S MANUAL
The history buffer flushes status pins denote how many instructions are flushed from
the history buffer this clock due to an
There is one special case when although queue flush information is expected on the
VF pins, (according to the last value on the VF pins), regular instruction type informa-
tion is reported. The only instruction type information that can appear in this case is VF
= 111, branch (direct or indirect) NOT taken. Since the maximum queue flushes pos-
sible is five, it is easy to identify this special case.
When entering debug mode an interrupt/exception taken is reported on the VF pins,
(VF = 100) and a cycle marked with the program trace cycle is made visible externally.
When the CPU is in debug mode, the VF pins equal ‘000’ and the VFLS pins equal
‘11’. For more information on debug mode refer to
face
If VSYNC is asserted/negated while the CPU is in debug mode, this information is re-
ported as the first VF pins report when the CPU returns to regular mode. If VSYNC
was not changed while in debug mode. the first VF pins report will be of an indirect
branch taken (VF = 101), suitable for the rfi instruction that is being issued. In both
/
MPC556
VFLS[0:1]
00
01
10
11
NOTES:
Table 21-2 VF Pins Queue Flush Encodings
VF[0:2]
000
001
010
011
100
101
110
111
1. Refer to
Freescale Semiconductor, Inc.
For More Information On This Product,
0 instructions flushed from history queue
1 instruction flushed from history queue
2 instructions flushed from history queue
Used for debug mode indication (FREEZE). Program trace ex-
ternal hardware should ignore this setting.
Table 21-3 VFLS Pin Encodings
0 instructions flushed from instruction queue
1 instruction flushed from instruction queue
2 instructions flushed from instruction queue
3 instructions flushed from instruction queue
4 instructions flushed from instruction queue
5 instructions flushed from instruction queue
Reserved
Instruction type information
Table
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21-1.
History Buffer Flush Information
Queue Flush Information
exception.Table 21-3
1
21.4 Development System Inter-
shows VFLS encodings.
MOTOROLA
21-4