MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 707

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.3.1 Internal Watchpoints and Breakpoints
MPC555
USER’S MANUAL
This section describes the internal breakpoints and watchpoints support of the CPU.
For information on external breakpoints support refer to
Interface
Internal breakpoint and watchpoint support is based on eight comparators comparing
information on instruction and load/store cycles, two counters, and two AND-OR logic
structures. The comparators perform compare on the Instruction address (I-address),
on the load/store address (L-address) and on the load/store data (L-data).
The comparators are able to detect the following conditions: equal, not equal, greater
than, less than (greater than or equal and less than or equal are easily obtained from
these four conditions, for more information refer to
Types). Using the AND-OR logic structures “in range” and “out of range” detections
(on address and on data) are supported. Using the counters, it is possible to program
a breakpoint to be recognized after an event was detected a predefined number of
times.
The L-data comparators can operate on fix point data of load or store. When operating
on fix point data the L-data comparators are able to perform compare on bytes, half-
words and words and can treat numbers either as signed or as unsigned values.
The comparators generate match events. The match events enter the instruction
AND-OR logic where the instruction watchpoints and breakpoint are generated. The
instruction watchpoints, when asserted, may generate the instruction breakpoint. Two
of them may decrement one of the counters. If one of the instruction watchpoints ex-
pires in a counter that is counting, the instruction breakpoint is asserted.
The instruction watchpoints and the load/store match events (address and data) enter
the load/store AND-OR logic where the load/store watchpoints and breakpoint are
generated. The load/store watchpoints, when asserted, may generate the load/store
breakpoint or they may decrement one of the counters. When a counter that is count-
ing one of the load/store watchpoints expires, the load/store breakpoint is asserted.
Watchpoints progress in the machine and are reported on retirement. Internal break-
points progress in the machine until they reach the top of the history buffer when the
machine branches to the breakpoint exception routine.
In order to enable the user to use the breakpoint features without adding restrictions
on the software, the address of the load/store cycle that generated the load/store
breakpoint is not stored in the DAR (data address register), like other load/store type
exceptions. In case of a load/store breakpoint, the address of the load/store cycle that
generated the breakpoint is stored in an implementation-dependent register called the
BAR (breakpoint address register).
Key features of internal watchpoint and breakpoint support are:
• Four I-address comparators (each supports equal, not equal, greater than, less
• Two L-address comparators (each supports equal, not equal, greater than, less
/
than)
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21.3.1.6 Generating Six Compare
21.4 Development System
MOTOROLA
21-11