MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 140

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

LR — Link Register
MSB
3.7.6 Link Register (LR)
MPC555
USER’S MANUAL
0
Bit(s)
25:31
3:24
0
1
2
The bit definitions for XER, shown in
struction considered as a whole, not on intermediate results. For example, the result
of the Subtract from Carrying (subfcx) instruction is specified as the sum of three val-
ues. This instruction sets bits in the XER based on the entire operation, not on an in-
termediate sum.
In most cases, reserved fields in registers are ignored when written to and return zero
when read. However, XER[16:23] are set to the value written to them and return that
value when read.
The 32-bit link register supplies the branch target address for the Branch Conditional
to Link Register (bclrx) instruction, and can be used to hold the logical address of the
instruction that follows a branch and link instruction.
Note that although the two least-significant bits can accept any values written to them,
they are ignored when the LR is used as an address.
Both conditional and unconditional branch instructions include the option of placing the
effective address of the instruction following the branch instruction in the LR. This is
done regardless of whether the branch is taken.
1
2
/
BYTES
3
MPC556
Name
SO
OV
CA
—
4
5
Table 3-10 Integer Exception Register Bit Definitions
Summary Overflow (SO) — The summary overflow bit is set whenever an instruction sets the
overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered
by compare instructions or other instructions that cannot overflow.
Overflow (OV) — The overflow bit is set to indicate that an overflow has occurred during exe-
cution of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out
of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by
compare instructions or other instructions that cannot overflow.
Carry (CA) — In general, the carry bit is set to indicate that a carry out of bit 0 occurred during
execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract
from extended instructions set CA to one if there is a carry out of bit 0, and clear it otherwise.
The CA bit is not altered by compare instructions or other instructions that cannot carry, except
that shift right algebraic instructions set the CA bit to indicate whether any ‘1’ bits have been
shifted out of a negative quantity.
Reserved
This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
6
7
8
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For More Information On This Product,
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CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
RESET: UNCHANGED
Branch Address
Table
3-10, are based on the operation of an in-
Description
MOTOROLA
SPR 8
3-18
LSB
31