MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 266

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.4 System Clock During PLL Loss of Lock
8.5 Low-Power Divider
MPC555
USER’S MANUAL
Where MF = the value stored on MF[0:11]. This is one less than the desired frequency multiplication factor.
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external
clock source is generating the system clock. In this case, if loss of lock is detected and
the LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock
source continues to function as the PLL’s output clock. The USIU timers can operate
with the input clock to the PLL, so that these timers are not affected by the PLL loss of
lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MCU can switch to the backup clock by
setting the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode
enable (LME) bit in the SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example,
if LOLRE is set) disables the PLL output clock until the lock condition is met. During
hard reset, the STBUC bit is set as long as the PLL lock condition is not met and clears
when the PLL is locked. If STBUC and LME are both set, the system clock switches to
the backup clock, and the chip operates in limp mode until STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK
is sent to a low-power divider block.) This block generates all other clocks in normal
operation, but has the ability to divide the output frequency of the VCO before it gen-
erates the general system clocks sent to the rest of the MPC555 / MPC556. The PLL
System Frequency (FREQ
The purpose of the low-power divider block is to allow the user to reduce and restore
the operating frequencies of different sections of the MPC555 / MPC556 without losing
the PLL lock. Using the low-power divider block, the user can still obtain full chip op-
eration, but at a lower frequency. This is called gear mode. The selection and speed
of gear mode can be changed at any time, with changes occurring immediately.
The low-power divider block is controlled in the system clock control register (SCCR).
The default state of the low-power divider is to divide all clocks by one. Thus, for a 40-
MHz system, the general system clocks are each 40 MHz.
/
0 < MF + 1 < 4
MF + 1 ≥ 4
MPC556
When the VCO is the system clock source, chip operation is unpre-
dictable while the PLL is unlocked. Note further that a switch to the
backup clock is possible only if the LME bit in the SCCR is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS AND POWER CONTROL
SYS
Go to: www.freescale.com
) is always divided by at least 2.
(680 x (MF + 1) – 120) pF
1100 x (MF + 1) pF
Rev. 15 October 2000
NOTE
MOTOROLA
8-6