MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 644

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

18.2 DPTRAM Configuration and Block Diagram
18.3 Programming Model
MPC555
USER’S MANUAL
The DPTRAM module consists of two separately addressable sections. The first is a
set of memory-mapped control and status registers used for configuration (DPTMCR,
RAMBAR, MISRH, MISRL, MISCNT) and testing (DPTTCR) of the DPTRAM array.
The second section is the array itself.
All DPTRAM module control and status registers are located in supervisor data space.
User reads or writes of these will result in a bus error.
When the TPU3 is using the RAM array for microcode control store, none of these con-
trol registers have any effect on the operation of the RAM array.
All addresses within the 64-byte control block will respond when accessed properly.
Unimplemented addresses will return zeros for read accesses. Likewise, unimple-
mented bits within registers will return zero when read and will not be affected by write
operations.
Table 18-1
are offsets from the base address for the module. Refer to
• Includes built in check logic which scans the array contents and calculates the
• IMB3 bus interface
• Two TPU3 interface units
• Bytes, half-word or word accessible
/
RAM signature
MPC556
shows the DPTRAM control and status registers. The addresses shown
RAM Mode
Freescale Semiconductor, Inc.
RAM
TPU
TPU
Figure 18-1 DPTRAM Configuration
For More Information On This Product,
DUAL-PORT TPU RAM (DPTRAM)
Go to: www.freescale.com
Rev. 15 October 2000
TPU Microcode Mode
1.3 MPC555 / MPC556 Ad-
RAM
TPU
TPU
Local Bus
Local Bus
MOTOROLA
18-2