MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 395

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.7 L-Bus Show Cycle Support
11.7.1 Programming Show Cycles
11.7.2 Performance Impact
MPC555
USER’S MANUAL
The L2U module provides support for L-bus show cycles. L-bus show cycles are ex-
ternal visibility cycles that reflect activity on the L-bus that would otherwise not be vis-
ible to the external bus. L-bus show cycles are software controlled.
L-bus show cycles are disabled during reset and must be configured by writing the ap-
propriate bits in the L2U_MCR control register. L-bus show cycles are programmed by
setting the LSHOW[0:1] bits in the L2U_MCR. The
tions of the LSHOW[0:1] bits.
When show cycles are enabled in the L2U module, there is a performance penalty on
the L-bus. This occurs because the L2U module does not support more than one ac-
cess being processed at any time. To ensure that only one access at a time can be
NOTES:
Reserved Location On
1. If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write
2. If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it
3. If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request
/
access from completing. In this case, the L2U will drive cancel-reservation signal back to the core as
soon as it comes to know that the alternate master on the U-bus has touched the reserved location.
communicates to the core that the current write has been aborted by the slave with no side effects.
on the U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination
signals and it communicates to the core if the current write has been aborted by the slave with no side
effects.
MPC556
LSHOW
External Bus
00
01
10
11
U-bus
L-bus
IMB3
Freescale Semiconductor, Inc.
Table 11-2 Reservation Snoop Support
Table 11-3 L2U_MCR LSHOW Modes
For More Information On This Product,
Show address and data of all L-bus space read and write cycles
L-BUS TO U-BUS INTERFACE (L2U)
Intruding Alternate Master
Show address and data of all L-bus space write cycles
Go to: www.freescale.com
IMB3-Master
Rev. 15 October 2000
Ext-Master
U-Master
U-Master
U-Master
U-Master
L-Master
L-Master
L-Master
L-Master
Reserved (Disable L-bus show cycles)
Disable L-bus show cycles
Action
Request to cancel the reservation.
Request to cancel the reservation.
Block stwcx
Block stwcx
Block stwcx
Block stwcx
Transfer Status
Block stwcx
Block stwcx
Transfer Status
Table 11-3
Action Taken on stwcx cycle
2
3
shows the configura-
MOTOROLA
1
11-9