MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 165

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction
3.14.5 Timebase
3.15 POWERPC Operating Environment Architecture (OEA)
3.15.1 Branch Processor Registers
3.15.1.1 Machine State Register (MSR)
3.15.1.2 Branch Processors Instructions
3.15.2 Fixed-Point Processor
3.15.2.1 Special Purpose Registers
MPC555
USER’S MANUAL
When executing an eieio instruction, the load/store unit will wait until all previous ac-
cesses have terminated before issuing cycles associated with load/store instructions
following the eieio instruction.
A description of the timebase register may be found in
URATION AND PROTECTION
TROL.
The MPC555 / MPC556 has an internal memory space that includes memory-mapped
control registers and internal memory used by various modules on the chip. This mem-
ory is part of the main memory as seen by the MPC555 / MPC556 but cannot be ac-
cessed by any external system master.
The floating-point exception mode encoding in the MPC555 / MPC556 core is as fol-
lows:
The SF bit is reserved set to zero
The IP bit initial state after reset is set as programmed by the reset configuration as
specified by the USIU specification.
The MPC555 / MPC556 implements all the instructions defined for the branch proces-
sor in the UISA in the hardware.
• Unsupported Registers — The following registers are not supported by the
/
MPC555 / MPC556: SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U,
IBAT2L, IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L,
MPC556
Table 3-23 Floating-Point Exception Mode Encoding
Ignore exceptions
Precise
Precise
Precise
Freescale Semiconductor, Inc.
For More Information On This Product,
Mode
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
and in
SECTION 8 CLOCKS AND POWER CON-
:
FE0
0
0
1
1
SECTION 6 SYSTEM CONFIG-
FE1
0
1
0
1
MOTOROLA
3-43