MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 421

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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13.7 External Multiplexing Operation
MPC555
USER’S MANUAL
Since port B is input-only, a data direction register is not needed. Read operations on
the reserved bits in DDRQA return zeros, and writes have no effect. Refer to
Port Data Direction Register
External multiplexers concentrate a number of analog signals onto a few inputs to the
analog converter. This is helpful in applications that need to convert more analog sig-
nals than the A/D converter can normally provide. External multiplexing also puts the
multiplexer closer to the signal source. This minimizes the number of analog signals
that need to be shielded due to the close proximity of noisy, high-speed digital signals
near the MCU.
The QADC64 can use from one to four external multiplexers to expand the number of
analog signals that may be converted. Up to 32 analog channels can be converted
through external multiplexer selection. The externally multiplexed channels are auto-
matically selected from the channel field of the CCW table, the same as internally mul-
tiplexed channels.
All of the automatic queue features are available for externally and internally multi-
plexed channels. The software selects externally multiplexed mode by setting the
MUX bit in QACR0.
Figure 13-3
to the QADC64. The external multiplexers select one of eight analog inputs and con-
nect it to one analog output, which becomes an input to the QADC64. The QADC64
provides three multiplexed address signals (MA[2:0]), to select one of eight inputs.
These outputs are connected to all four multiplexers. The analog output of each mul-
tiplexer is each connected to one of four separate QADC64 inputs — ANw, ANx, ANy,
and ANz.
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Caution should be exercised when mixing digital and analog inputs.
This should be minimized as much as possible. Input pin rise and fall
times should be as large as possible to minimize AC coupling effects.
shows the maximum configuration of four external multiplexers connected
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
for register and bit descriptions.
Rev. 15 October 2000
MOTOROLA
13.12.5
13-9

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