MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 877

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

F.1 Introduction
MPC555 / MPC556
USER’S MANUAL
NOTES:
RCPU Load/Store
RCPU Instruction
CPUs are active)
Peripheral Mode
(ony ext. master
(both ext. & int.
Table F-1
combinations. The clock values show the number of clocks from the moment an ad-
dress is valid on a specific bus, until data is back on that same bus. The following as-
sumptions were used when compiling the information:
1. “/” comes for on/off page flash access.
2. N is the number of clocks from external address valid till external data valid in the case of read cycle. In the case
3. Assuming BBC is parked on U-BUS.
4. Until address is valid on external pins
Slave Mode
of zero wait states, N = 2.
is active)
Fetches
• The arbitration time was ignored. The values assume that the bus (or buses) in-
• The UIMB works in a mode of 1:1. This is relevant for IMB accesses values. In
• The basic delay of external bus to U-bus is four clocks (external master case).
• All IMB accesses are assumed to be 16-bit accesses only. If 32-bit accesses are
volved in a transaction was in the IDLE state when the transaction needs that bus.
the case of 2:1 mode, the clock latency for a cycle on the IMB should be doubled.
(each IMB access takes two clocks.)
used, then each such IMB access is split into two separate 16-bit cycles with nor-
mal IMB performance for each.
lists all possible memory access timing to internal and external memory
Table F-1 Memory Access Times Using Different Buses
2-1-1-1-1...
FLASH
3/4
4/5
5/6
Freescale Semiconductor, Inc.
1
For More Information On This Product,
MEMORY ACCESS TIMING
INTERNAL
RAM
MEMORY ACCESS TIMING
3
1
6
7
Go to: www.freescale.com
3
Rev. 15 October 2000
APPENDIX F
IMB
6
7
8
-
SIU
5
6
7
-
External
Memory
Mapped
Internal
4+N
EXTERNAL RAM/
2+N
2
FLASH
mapped
Memory
Internal
Non-
4+N
2+N
Write
SHOW CYCLE
2
-
MOTOROLA
Read
1
2
4
F-1