MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 222

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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Price
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MPC555LFMZP40
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6.8 Real-Time Clock (RTC)
MPC555
USER’S MANUAL
generate a maskable interrupt when the time base counter reaches the value pro-
grammed in one of the two reference registers. The period of the TB depends on the
driving frequency. In the MPC555 / MPC556, the TB is clocked by the TMBCLK clock.
The period for the TB is:
The state of the time base is not affected by any resets and should be initialized by
software. Reads and writes of the TB are restricted to special instructions. Separate
special-purpose registers are defined in the MPC555 / MPC556 architecture for read-
ing and writing the time base. For the MPC555 / MPC556 implementation, it is not pos-
sible to read or write the entire TB in a single instruction. Therefore, the mttb and mftb
instructions are used to move the lower half of the time base (TBL) while the mttbu
and mftbu instructions are used to move the upper half (TBU).
Two reference registers are associated with the time base: TBREF0 and TBREF1. A
maskable interrupt is generated when the TB count reaches to the value programmed
in one of the two reference registers. Two status bits in the time base control and sta-
tus register (TBSCR) indicate which one of the two reference registers generated the
interrupt.
Refer to
base registers. Refer to
ence Manual (RCPURM/AD)
MPC556 time base.
The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to
the operating system and application software. It is clocked by the pitrtclk clock.The
counter is not affected by reset and operates in all low-power modes. It is initialized by
software. The RTC can be programmed to generate a maskable interrupt when the
time value matches the value programmed in its associated alarm register. It can also
be programmed to generate an interrupt once a second. A control and status register
is used to enable or disable the different functions and to report the interrupt source.
/
MPC556
6.13.4 System Timer Registers
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
For More Information On This Product,
3.9.4 Time Base Facility (TB) — OEA
Go to: www.freescale.com
Rev. 15 October 2000
for additional information regarding the MPC555 /
T
TB
=
for diagrams and bit descriptions of time
---------------------- -
F
tmbclk
2 64
and to
RCPU Refer-
MOTOROLA
6-14

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