MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 234

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

*IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is
6.13.2.3 SIU Interrupt Edge Level Register (SIEL)
6.13.2.4 SIU Interrupt Vector Register
MPC555
USER’S MANUAL
SIEL — SIU Interrupt Edge Level Register
SIVEC — SIU Interrupt Vector
MSB
MSB
ED0
a non-maskable interrupt.
16
16
0
0
0
0
0
0
RESET:
RESET:
RESET:
RESET:
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external
interrupt request. The EDx bit, if set, specifies that a falling edge in the corresponding
IRQ line will be detected as an interrupt request. When the EDx bit is 0, a low logical
level in the IRQ line will be detected as an interrupt request. The WMx (wake-up mask)
bit, if set, indicates that an interrupt request detection in the corresponding line causes
the MPC555 / MPC556 to exit low-power mode.
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the
unmasked interrupt source of the highest priority level. The SIVEC can be read as ei-
ther a byte, half word, or word. When read as a byte, a branch table can be used in
which each entry contains one instruction (branch). When read as a half-word, each
entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table.
WM0
17
17
/
0
1
0
0
1
0
MPC556
ED1
18
18
0
2
0
0
2
1
INTERRUPT CODE
WM1
19
19
0
3
0
0
3
1
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
ED2
20
20
0
4
0
0
4
1
For More Information On This Product,
WM2
21
21
0
5
0
0
5
1
Go to: www.freescale.com
Rev. 15 October 2000
ED3
22
22
0
6
0
0
6
0
WM3
RESERVED
RESERVED
23
23
0
7
0
0
7
0
ED4
24
24
0
8
0
0
8
0
WM4
25
25
0
9
0
0
9
0
ED5
26
10
26
10
0
0
0
0
WM5
RESERVED
27
11
27
11
0
0
0
0
ED6
28
12
28
12
0
0
0
0
WM6
29
13
29
13
0
0
0
0
0x2F C01C
0x2F C018
MOTOROLA
ED7
30
14
30
14
0
0
0
0
WM7
LSB
LSB
31
15
31
15
6-26
0
0
0
0