MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 343

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.10.2 Termination Signals Protocol Summary
9.5.11 Bus Operation in External Master Modes
MPC555
USER’S MANUAL
causes a transfer error acknowledge. See
Size.
Table 9-9
provided by the slave device that is addressed by the initiated transfer.
When an external master takes ownership of the external bus and the MPC555 /
MPC556 is programmed for external master mode operation, the external master can
access the internal space of the MPC555 / MPC556 (see
Modes). In an external master mode, the external master owns the bus, and the direc-
tion of most of the bus signals is inverted, relative to its direction when the MPC555 /
MPC556 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an
external master access. The access is directed to the internal bus only if the input ad-
dress matches the internal address space. The access is terminated with one of the
followings outputs: TA, TEA, or RETRY. If the access completes successfully, the
MPC555 / MPC556 asserts TA, and the external master can proceed with another ex-
ternal master access or relinquish the bus. If an address or data error is detected in-
ternally, the MPC555 / MPC556 asserts TEA for one clock. TEA should be negated
before the second rising edge after it is sampled asserted in order to avoid the detec-
tion of an error for the next bus cycle initiated. TEA is an open drain pin, and the ne-
gation timing depends on the attached pullup. The MPC555 / MPC556 asserts the
RETRY signal for one clock in order to retry the external master access.
If the address of the external access does not match the internal memory space, the
internal memory controller can provide the chip-select and control signals for accesses
that belong to one of the memory controller regions. This feature is explained in
TION 10 MEMORY
Figure 9-34
accesses.
Asserted
Negated
Negated
TEA
/
MPC556
summarizes how the MPC555 / MPC556 recognizes the termination signals
and
Figure 9-35
Asserted
Negated
TA
Freescale Semiconductor, Inc.
Table 9-9 Termination Signals Protocol
X
CONTROLLER.
For More Information On This Product,
EXTERNAL BUS INTERFACE
illustrate the basic flow of read and write external master
Go to: www.freescale.com
Rev. 15 October 2000
Asserted
RETRY
X
X
9.5.2.3 Single Beat Flow with Small Port
Normal transfer termination
Transfer error termination
Retry transfer termination
Action
6.2 External Master
MOTOROLA
SEC-
9-47