MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 736

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.5.6.9 Serial Data Into Development Port
Table 21-13 Debug Instructions / Data Shifted Into Development Port Shift Register
MPC555
USER’S MANUAL
NOTES:
Start
start/ready bit, a mode/status bit, a control/status bit, and 32 bits of data. All instruc-
tions and data for the CPU are transmitted with the mode bit cleared indicating a 32-
bit data field. The encoding of data shifted into the development port shift register
(through the DSDI pin) is shown below in
1
1
1
1
1
1. Refer to
Data values in the last two functions other than those specified are reserved.
All transmissions from the debug port on DSDO begin with a “0” or “ready” bit. This
indicates that the CPU is trying to read an instruction or data from the port. The exter-
nal development tool must wait until it sees DSDO go low to begin sending the next
transmission.
The control bit differentiates between instructions and data and allows the develop-
ment port to detect that an instruction was entered when the CPU was expecting data
and vice versa. If this occurs a sequence error indication is shifted out in the next serial
transmission.
The trap enable function allows the development tool to transfer data to the trap enable
control register.
The debug port command function allows the development tool to either negate break-
point requests, reset the processor, activate or deactivate the fast down load proce-
dure.
The NOP function provides a null operation for use when there is data or a response
to be shifted out of the data register and the appropriate next instruction or command
will be determined by the value of the response or data shifted out.
In debug mode the 35 bits of the development port shift register are interpreted as a
/
Mode
MPC556
0
0
1
1
1
Table 21-10
Control
0
1
0
1
1
Freescale Semiconductor, Inc.
Trap enable
For More Information On This Product,
0011111
Bits 0:6
0
DEVELOPMENT SUPPORT
Go to: www.freescale.com
1
Instruction / Data (32 Bits)
Rev. 15 October 2000
CPU Instruction
CPU Data
.
Table 21-13
Bits 7:31
Not exist
Not exist
Not exist
Negate breakpoint requests
Transfer Instruction
Control Register
Transfer data to
Transfer Data
Trap Enable
to the CPU.
Function
to CPU
to CPU
nop
MOTOROLA
21-40