MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 392

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Program the region base address in the L2U_RBAx registers to the lower boundary of
the region specified by the corresponding L2U_RAx[RS] field. If the region base ad-
dress does not correspond to the boundary of the block size programmed in the
L2U_RAx, the DMPU snaps the region base to the lower boundary of that block. For
example, if the block size is programmed to 16 Kbytes for region zero (i.e.
L2U_RA0[RS] = 0 x 3) and the region base address is programmed to 0x1FFF(i.e.,
L2U_RBA0[RBA] = 0 x 1), then the effective base address of region zero is 0 x 0. See
Figure
It is the user’s responsibility to program only legal region sizes. The L2U does not
check whether the value is legal. If the user programs an illegal region size, the region
calculation may not be successful.
/
MPC556
0x0000 0000
0x0000 1FFF
0x0000 3FFF
0x0000 5FFF
11-3.
The appropriate DMPU registers must be programmed before the
MSR[DR] bit is set. Otherwise, DMPU operation is not guaranteed.
L2U_RBA0
L2U_RBA1
L2U_RBA2
L2U_RBA3
L2U_GRA
L2U_RA0
L2U_RA1
L2U_RA2
L2U_RA3
Figure 11-3 Region Base Address Example
Name
Freescale Semiconductor, Inc.
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
Table 11-1 DMPU Registers
(16 Kbytes)
Region Base Address Register 0
Region Base Address Register 1
Region Base Address Register 2
Region Base Address Register 3
Region Attribute Register 0
Region Attribute Register 1
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
region 0
Go to: www.freescale.com
Rev. 15 October 2000
CAUTION
.
Description
Resulting Region
Actual Programmed Region
MOTOROLA
11-6