MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 302

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Transfer acknowledge
Transfer error
Signal Name
acknowledge
Burst inhibit
DATA[0:31]
Data bus
/
MPC556
TEA
TA
BI
Table 9-1 MPC555 / MPC556 SIU Signals (Continued)
Freescale Semiconductor, Inc.
Pins
32
1
1
1
For More Information On This Product,
EXTERNAL BUS INTERFACE
Active
LOW
High
Go to: www.freescale.com
Low
Low
Transfer Cycle Termination
Rev. 15 October 2000
I/O
Data
O
O
O
O
I
I
I
I
The data bus has the following byte lane assign-
ments:
Data Byte
DATA[0:7]
DATA[8:15]
DATA[16:23] 2
DATA[24:31] 3
Driven by the MPC555 / MPC556 when it owns the
external bus and it initiated a write transaction to a
slave device. For single beat transactions, the byte
lanes not selected for the transfer by ADDR[30:31]
and TSIZ[0:1] do not supply valid data.
In addition, the MPC555 / MPC556 drives DATA[0:31]
when an external master owns the external bus and
initiated a read transaction to an internal slave mod-
ule.
Driven by the slave in a read transaction. For single
beat transactions, the MPC555 / MPC556 does not
sample byte lanes that are not selected for the trans-
fer by ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave mod-
ule drives DATA[0:31].
Driven by the slave device to which the current trans-
action was addressed. Indicates that the slave has re-
ceived the data on the write cycle or returned data on
the read cycle. If the transaction is a burst, TA should
be asserted for each one of the transaction beats.
Driven by the MPC555 / MPC556 when the slave de-
vice is controlled by the on-chip memory controller or
when an external master initiated a transaction to an
internal slave module.
Driven by the slave device to which the current trans-
action was addressed. Indicates that an error condi-
tion has occurred during the bus cycle.
Driven by the MPC555 / MPC556 when the internal
bus monitor detected an erroneous bus condition, or
when an external master initiated a transaction to an
internal slave module and an internal error was de-
tected.
Driven by the slave device to which the current trans-
action was addressed. Indicates that the current slave
does not support burst mode.
Driven by the MPC555 / MPC556 when the slave de-
vice is controlled by the on-chip memory controller.
the MPC555 / MPC556 also asserts BI for any exter-
nal master burst access to internal MPC555 /
MPC556 memory space.
0
1
Byte Lane
Description
MOTOROLA
9-6