MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 228

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
NOTES:
Bit(s)
13:14
17:18
20:21
22:23
25:31
9:10
1:3
4:7
11
12
15
16
19
24
0
8
1. WE/BE is selected per memory region by WEBS in the approprite BR register in the memory controller.
/
MPC556
DSHW
DBGC
ATWC
DBPC
MLRC
MTSC
Name
EARB
EARP
RCTX
GPC
DLK
SC
—
—
—
—
External arbitration
0 = Internal arbitration is performed
1 = External arbitration is assumed
External arbitration request priority. This field defines the priority of an external master’s arbitra-
tion request. This field is valid when EARB is cleared. Refer to
details.
Reserved
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and flash EEPROM). This field is locked by the DLK bit. Note that instruc-
tion show cycles are programmed in the ICTRL and L-bus data show cycles (to SRAM) are pro-
grammed in the L2UMCR.
0 = Disable show cycles for all internal data cycles
1 = Show address and data of all internal data cycles
Debug pins configuration. Refer to
Debug port pins configuration. Refer to
Address write type enable configuration. This bit configures the pins to function as byte write en-
ables or address types for debugging purposes.
0 = WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 = WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
This bit configures the pins as shown in
Debug register lock
0 = Normal operation
1 = SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
Reserved
Single-chip select. This field configures the functionality of the address and data buses. Chang-
ing the SC field while external accesses are performed is not supported. Refer to
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as
RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal
that supports the low-power modes.
0 = RSTCONF/TEXP functions as RSTCONF
1 = RSTCONF/TEXP functions as TEXP
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to
Reserved
Memory transfer start control.
0 = IRQ[2]/CR/SGPIOC[2]/MTS functions according to the MLRC bits setting
1 = IRQ[2]/CR/SGPIOC[2]/MTS functions as MTS
Reserved
asserted.
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
Table 6-5 SIUMCR Bit Descriptions
For More Information On This Product,
Go to: www.freescale.com
Table
Rev. 15 October 2000
6-10.
Table
Table
Table
Description
6-6.
6-7.
6-8.
1
9.5.6.4 Internal Bus Arbiter
MOTOROLA
Table
6-9.
6-20
for