MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 380

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.8.2 Memory Controller Status Registers (MSTAT)
10.8.3 Memory Controller Base Registers (BR0 – BR3)
* Reset value is determined by the value on the internal data bus during reset.
** The BR0 Reset value is determined by the value on the internal data bus during reset (reset-configuration word). The
MPC555
USER’S MANUAL
MSTAT — Memory Controller Status Register
BR0 – BR3 — Memory Controller Base Registers 0 – 3 0x2F C100, C108, C110, C118
HARD RESET:
Bit(s)
12:15
MSB
MSB
8:11
reset value of the V bit of BR1-3 = 0.
BA
0:7
16
U
U
0
0
0
17
U
WPER0 –
U
/
1
0
1
WPER3
MPC556
Name
—
—
AT
18
U
U
2
0
2
Reserved
Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
the user to read this register if TA is not asserted during a write cycle. WPERx is cleared by writ-
ing one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
Reserved
RESERVED
19
U
U
3
0
3
Freescale Semiconductor, Inc.
20
U
4
0
4
ID[4:5]*
Table 10-6 MSTAT Bit Descriptions
For More Information On This Product,
PS
21
U
5
0
5
Go to: www.freescale.com
MEMORY CONTROLLER
SERV
Rev. 15 October 2000
RE-
ED
22
U
6
0
6
0
WP
23
U
7
0
7
HRESET
HRESET
0
BA
,
,
WPER
RESERVED
24
U
8
0
0
8
0
Description
WPER
25
U
9
1
0
9
0
WPER
WEBS TBDIP LBDIP SETA
10
10
26
U
2
0
0
WPER
11
11
27
U
3
0
0
12
12
28
U
0
RESERVED
13
13
29
U
0
0
0x2F C178
MOTOROLA
14
14
30
U
BI
0
1
10-28
ID3**
LSB
LSB
15
15
31
U
0
V