MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 327

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.6.1 Bus Request
MPC555
USER’S MANUAL
ecute a new cycle, the master must re-arbitrate before a new cycle can be executed.
The MPC555 / MPC556, however, guarantees data coherency for access to a small
port size and for decomposed bursts. This means that the MPC555 / MPC556 will not
release the bus before the completion of the transactions that are considered atomic.
Figure 9-23
The potential bus master asserts BR to request bus mastership. BR should be negated
as soon as the bus is granted, the bus is not busy, and the new master can drive the
bus. If more requests are pending, the master can keep asserting its bus request as
long as needed. When configured for external central arbitration, the MPC555 /
MPC556 drives this signal when it requires bus mastership. When the internal on-chip
arbiter is used, this signal is an input to the internal arbiter and should be driven by the
external bus master.
/
2. Assert BB to become next master
1. Assert BR
3. Negate BR
1. Wait for BB to be negated.
1. Perform data transfer
1. Negate BB
MPC556
Acknowledge Bus Mastership
Release Bus Mastership
Operate as Bus Master
Requesting Device
Request the Bus
describes the basic protocol for bus arbitration.
Freescale Semiconductor, Inc.
Figure 9-23 Bus Arbitration Flowchart
For More Information On This Product,
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
1. Negate BG (or keep asserted to park
1. Assert BG
bus master)
Terminate Arbitration
Grant Bus Arbitration
Arbiter
MOTOROLA
9-31