MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 674

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC555LFMZP40
Manufacturer:
MOTOLOLA
Quantity:
853
Part Number:
MPC555LFMZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC555LFMZP40
Manufacturer:
MOT
Quantity:
2
Part Number:
MPC555LFMZP40R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
19.5.2 Program Margin Reads
MPC555
USER’S MANUAL
State
S5
The CMF EEPROM provides a program margin read with electrical margin for the pro-
gram state. Program margin reads provide sufficient margin to assure specified data
retention. The program margin read is enabled when SES = 1 and a programming
write has occurred. To increase the access time of the program margin read, the off-
page access time is four clocks instead of the usual two-clock off-page read access
time. The program margin read and subsequent on-page program verify reads return
a one for any bit that has not been completely programmed. Bits that the programming
write left in the non-programmed state return zero when read. Bits that have completed
programming return zero when read and update the data in the programming page
buffer so that no further programming of those bits will occur. The program margin
read occurs during the off-page read. A program margin read must be performed for
all pages that are being programmed after each program pulse.
Current Data in the Pro-
NOTES:
gram Page Buffer
1. 0 = bit needs further programming
2. A “0” read during the margin read means that the bit does NOT need further programming. A “1” means
Program Margin Read Operation:
These reads determines if the state of the bits on
the selected page needs further modification by
the program operation. Once a bit is fully pro-
grammed, the data stored in the program page is
updated. No further programming occurs for that
bit, and the value read is a 0.
While it is not necessary to read all words on a
page to determine if another program pulse needs
to be applied, all pages being programmed must
be read once after each program pulse.
/
1 = bit does not need further programming
the bit needs to be programmed further.
MPC556
Table 19-9 Program Interlock State Descriptions (Continued)
0
0
1
1
Table 19-10 Results of Programming Margin Read
1
Freescale Semiconductor, Inc.
Mode
For More Information On This Product,
Current State of Bit
Programmed (0)
Programmed (0)
Erased (1)
Erased (1)
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
Data Read During
State
Next
S4
S1
Margin Read
1
0
0
0
T8
T9
Write EHV = 1
Write SES = 0 or a master reset.
2
Transition Requirement
Program Page Buffer
New Data for the
1
0
1
1
MOTOROLA
1
19-22

Related parts for MPC555LFMZP40