MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 382

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.8.4 Memory Controller Option Registers (OR0 – OR3)
MPC555
USER’S MANUAL
OR0 – OR3 — Memory Controller Option Registers 0 – 3
Bit(s)
17:19
21:22
MSB
AM*
0:16
HRESET: (OR[1:3]):
16
20
HRESET:
U
U
0
(OR[1:3])
0
0
HRESET
HRESET
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 2
(OR0)
(OR0)
17
U
U
/
1
0
0
MPC556
Name
CSNT
ATM
ACS
AM
ATM
18
U
U
2
0
0
Address mask. This field allows masking of any corresponding bits in the associated base regis-
ter. Masking the address bits independently allows external devices of different size address
ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the
corresponding address bit to be used in comparison with the address pins. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. This field can be read or written at anytime.
Following a system reset, the AM bits are reset in OR0.
Address type mask. This field masks selected address type bits, allowing more than one address
space type to be assigned to a chip-select. Any set bit causes the corresponding address type
code bits to be used as part of the address comparison. Any cleared bit masks the corresponding
address type code bit. Clear the ATM bits to ignore address type codes as part of the address
comparison. Note that the address type field uses only AT[0:2] and does not need AT[3] to define
the memory type space.
Following a system reset, the ATM bits are reset in OR0.
Chip-select negation time. Following a system reset, the CSNT bit is reset in OR0.
0 = CS/WE are negated normally.
1 = CS/WE are negated a quarter of a clock earlier than normal
Following a system reset, the CSNT bit is reset in OR0.
Address to chip-select setup. Following a system reset, the ACS bits are reset in OR0.
00 = CS is asserted at the same time that the address lines are valid.
01 = Reserved
10 = CS is asserted a quarter of a clock after the address lines are valid.
11 = CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are reset in OR0.
19
U
U
3
0
0
CSNT
Table 10-8 OR0 – OR3 Bit Descriptions
Freescale Semiconductor, Inc.
20
U
U
4
0
0
For More Information On This Product,
21
U
U
5
0
0
ACS
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
22
U
U
6
0
0
EHTR
23
U
U
7
0
0
AM*
,
24
U
U
8
0
1
Description
25
U
U
9
0
1
SCY
10
26
U
U
0
1
11
27
U
U
0
1
12
28
U
U
0x2F C104, C10C,
0
0
BSCY
3
13
29
- 1 = 7 [0b111]).
U
U
0
1
C114, C11C
MOTOROLA
14
30
U
U
0
1
TRLX
10-30
LSB
15
31
U
U
0
0