MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 702

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.2.4.2 Detecting the Trace Window Start Address
MPC555
USER’S MANUAL
ternal event of the CPU, it is possible to use the internal breakpoints together with de-
bug mode. This method is available only when debug mode is enabled. For more
information on debug mode refer to
The following is an example of steps that enable the user to synchronize the trace win-
dow to the CPU internal events:
When using back trace, latching the value of the status pins (VF and VFLS), and the
address of the cycles marked as program trace cycle, should start immediately after
the negation of reset. The start address is the first address in the program trace cycle
buffer.
When using window trace, latching the value of the status pins (VF and VFLS), and
the address of the cycles marked as program trace cycle, should start immediately af-
ter the first VSYNC is reported on the VF pins. The start address of the trace window
should be calculated according to first two VF pins reports.
Assuming that VF1 and VF2 are the two first VF pins reports and T1 and T2 are the
two addresses of the first two cycles marked with the program trace cycle attribute that
were latched in the trace buffer, use the following table to calculate the trace window
start address.
10. The hardware generates a breakpoint when the programmed event is detected
11. Negate VSYNC
12. Return to the regular code run (issue an rfi). The first report on the VF pins is a
13. The external hardware stops sampling the program trace information upon the
1. Enter debug mode, either immediately out of reset or using the debug mode re-
2. Program the hardware to break on the event that marks the start of the trace
3. Enable debug mode entry for the programmed breakpoint in the debug enable
4. Return to the regular code run (see
5. The hardware generates a breakpoint when the programmed event is detected
6. Program the hardware to break on the event that marks the end of the trace
7. Assert VSYNC
8. Return to the regular code run. The first report on the VF pins is a VSYNC (VF
9. The external hardware starts sampling the program trace information upon the
/
MPC556
quest
window using the control registers defined in
points Support
register (DER). See
and the machine enters debug mode (see
window
= 011).
report on the VF pins of VSYNC
and the machine enters debug mode
VSYNC (VF = 011)
report on the VF pins of VSYNC
Freescale Semiconductor, Inc.
For More Information On This Product,
21.7.12 Debug Enable Register
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21.4 Development System Interface
21.4.1.6 Exiting Debug
21.4.1.2 Entering Debug
21.3 Watchpoints and Break-
(DER))
Mode)
MOTOROLA
Mode)
21-6