MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 413

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.1 Overview
MPC555 / MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
USER’S MANUAL
The MPC555 / MPC556 includes two independent queued analog-to-digital converter
(QADC64) modules. For details of QADC64 operation not included in this section, re-
fer to the
The QADC64 consists of an analog front-end and a digital control subsystem, which
includes an intermodule bus (IMB3) interface block. Refer to
The analog section includes input pins, channel selection logic, an analog multiplexer,
and one sample-and-hold analog circuit. The analog conversion is performed by the
digital-to-analog converter (DAC) resistor-capacitor array, a high-gain comparator,
and a successive approximation register (SAR).
The digital control section contains the conversion sequencing logic. Also included are
the periodic/interval timer, control and status registers, the conversion command word
(CCW) table RAM, and the result word table RAM.
EXTERNAL
TRIGGERS
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
CONTROL
DIGITAL
QADC Reference Manual
IMB
MUX ADDRESS
EXTERNAL
Freescale Semiconductor, Inc.
INTERMODULE BUS
Figure 13-1 QADC64 Block Diagram
For More Information On This Product,
INTERFACE
Go to: www.freescale.com
COMMAND WORDS (CCW), 64 ENTRIES
Rev. 15 October 2000
QUEUE OF 10-BIT CONVERSION
ANALOG INPUT MULTIPLEXER AND
SECTION 13
DIGITAL PIN FUNCTIONS
(QADCRM/AD).
UP TO 16 ANALOG
INPUT PINS
10-BIT ANALOG TO DIGITAL CONVERTER
10-BIT RESULT TABLE,
Figure
REFERENCE
RESULT ALIGNMENT
INPUTS
10-BIT TO 16-BIT
64 ENTRIES
13-1.
ANALOG POWER
INPUTS
MOTOROLA
13-1