MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 653

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.1 Introduction
MPC555 / MPC556
USER’S MANUAL
The two CDR MoneT flash EEPROM modules (CMF) serve as electrically program-
mable and erasable non-volatile memory (NVM) to store system program and data.
The modules are designed to be used with the unified bus (U-bus). The CMF arrays
use Motorola’s one-transistor (MoneT) bit cell technology. The MPC555 / MPC556’s
total 448-Kbytes of flash EEPROM non-volatile memory are distributed between two
CMF EEPROM modules: a 256-Kbyte array and a 192-Kbyte array. The erase block
size is 32 Kbytes.
Each CMF EEPROM module is arranged into two major sections. The first section is
the flash EEPROM array used to store system program and data. The second section
is the bus interface unit (BIU) that controls access and operation of the array through
a standard U-bus interface and the external signals EPEE (external program or erase
enable) and VPP (supply program or erase power).
Each CMF EEPROM module array is divided into blocks to allow for independent
erase, access state, and protection from program and erase for each block. Informa-
tion is transferred to the CMF EEPROM through the U-bus a word (32 bits), half-word
(16 bits), or byte at a time.
The BIU accesses 32 bytes of information in the array at a time. These bytes are cop-
ied into a read-page buffer aligned to the low order addresses, ADDR[27:31]. Each
CMF module contains two non-overlapping page buffers. The first page buffer is as-
sociated with array blocks zero to three. The second page is associated with array
blocks four to seven (for CMF Module A), or blocks four to five (for CMF Module B).
Read access time for data in the page buffers (on-page read) is one system clock. The
read access time for a new page of data (off-page read) is two system clocks. To pre-
vent the BIU from accessing an unnecessary page from the array, the CMF EEPROM
monitors the U-bus address to determine whether the required information is in one of
the two current pages and whether the access is valid for the module.
Burst accesses are not supported by the CMF EEPROM. In normal operation, write
accesses to the CMF array are not recognized.
The CMF EEPROM module requires an external program or erase voltage (VPP) to
program or erase the array or any of its control register shadow bits. Special hardware
interlocks and the external signal EPEE protect the array from accidental enabling of
program and erase operation. The program and erase algorithms are implemented by
a series of writes to the CMF EEPROM registers and are under software control.
Freescale Semiconductor, Inc.
For More Information On This Product,
CDR MoneT FLASH EEPROM
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
SECTION 19
MOTOROLA
19-1