MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 688

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.9 Pin Descriptions
19.9.1 E
MPC555
USER’S MANUAL
Figure 19-6
The CMF modules use the following pins:
The EPEE bit monitors the state of the external program/erase enable, E
has a digital filter that requires two consecutive samples to be equal before the output
of the filter changes. The CMF samples E
E
PEE
• T1: Cleared censorship to no censorship
• T2: No censorship to information censorship
• T3: Information censorship, no censorship or unknown to cleared censorship
• T4: Cleared censorship to information censorship
• E
• V
• V
• V
/
Set CENSOR[0] or CENSOR[1].
Set CENSOR[0] and CENSOR[1].
clear CENSOR[0:1]. This is done only while the entire CMF array is erased.
Set both CENSOR[0] and CENSOR[1].
PEE
state until EHV is negated. This is shown in
MPC556
PEE
PP
DDF
SSF
Digital Filter
EPEE Pin’s
EPEE Pin = 0
Signal
Output = 0
Output = 1
Pin Filter
Pin Filter
@ ↑T2
illustrates the following CENSOR[0:1] transitions:
Figure 19-7 EPEE Digital Filter and Latch
Freescale Semiconductor, Inc.
For More Information On This Product,
EPEE Pin = 1
EPEE Pin = 0
EPEE Pin = 1
EPEE Pin = 0
@ ↑T2
@ ↑T2
@ ↑T2
@ ↑T2
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
EPEE Pin = 1
Output = 0
Output = 1
Pin Filter
Pin Filter
@ ↑T2
PEE
when EHV is asserted and holds the
Figure
19-7.
In
Latch
EHV
Out
PEE
EPEE
MOTOROLA
pin. E
19-36
PEE