MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 704

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.2.5 Instruction Fetch Show Cycle Control
21.3 Watchpoints and Breakpoints Support
MPC555
USER’S MANUAL
Instruction fetch show cycles are controlled by the bits in the ICTRL and the state of
VSYNC. The following table defines the level of fetch show cycles generated by the
CPU. For information on the fetch show cycles control bits refer to
Watchpoints, when detected, are reported to the external world on dedicated pins but
do not change the timing and the flow of the machine. Breakpoints, when detected,
force the machine to branch to the appropriate exception handler. The CPU supports
internal watchpoints, internal breakpoints, and external breakpoints.
Internal watchpoints are generated when a user programmable set of conditions are
met. Internal breakpoints can be programmed to be generated either as an immediate
result of the assertion of one of the internal watchpoints, or after an internal watchpoint
is asserted for a user programmable times. Programming a certain internal watchpoint
to generate an internal breakpoint can be done either in software, by setting the cor-
responding software trap enable bit, or on the fly using the serial interface implement-
ed in the development port to set the corresponding development port trap enable bit.
External breakpoints can be generated by any of the peripherals of the system, includ-
ing those found on the MPC555 / MPC556 or externally, and also by an external de-
velopment system. Peripherals found on the external bus use the serial interface of the
development port to assert the external breakpoint.
In the CPU, as in other RISC processors, saving/restoring machine state on the stack
during exception handling, is done mostly in software. When the software is in the mid-
dle of saving/restoring machine state, the MSR[RI] bit is cleared. Exceptions that occur
and that are handled by the CPU when the MSR[RI] bit is clear result in a non-restart-
able machine state. For more information refer to
In general, breakpoints are recognized in the CPU is only when the MSR[RI] bit is set,
which guarantees machine restartability after a breakpoint. In this working mode
breakpoints are said to be masked. There are cases when it is desired to enable
VSYNC
/
MPC556
X
X
X
0
1
A cycle marked with the program trace cycle attribute is generated for
any change in the VSYNC state (assertion or negation).
Control Bits ISCTRL[ISCT_SER]
Instruction Fetch Show Cycle
Freescale Semiconductor, Inc.
Table 21-5 Fetch Show Cycles Control
For More Information On This Product,
ISCTL
x00
x01
x10
x11
x11
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
All fetch cycles
All change of flow (direct & indirect)
All indirect change of flow
No show cycles are performed
All indirect change of flow
3.15.4 Interrupts
Show Cycles Generated
Table 21-5
MOTOROLA
21-8