MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 335

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.8.2 Burst Inhibit
9.5.8.3 Transfer Error Acknowledge
9.5.8.4 Termination Signals Protocol
MPC555
USER’S MANUAL
A slave sends the BI signal to the master to indicate that the addressed device does
not have burst capability. If this signal is asserted, the master must transfer in multiple
cycles and increment the address for the slave to complete the burst transfer. For a
system that does not use the burst mode at all, this signal can be tied low permanently.
The TEA signal terminates a bus cycle under one or more bus error conditions. The
current bus cycle must be aborted. This signal overrides any other cycle termination
signals, such as transfer acknowledge.
The transfer protocol was defined to avoid electrical contention on lines that can be
driven by various sources. To this end, a slave must not drive signals associated with
the data transfer until the address phase is completed and it recognizes the address
as its own. The slave must disconnect from signals immediately after it has acknowl-
edged the cycle and no later than the termination of the next address phase cycle. This
means that the termination signals must be connected to power through a pull-up re-
sistor to avoid the situation in which a master samples an undefined value in any of
these signals when no real slave is addressed.
Refer to
/
MPC556
MCU
Figure 9-27 Termination Signals Protocol Basic Connection
Figure 9-27
Freescale Semiconductor, Inc.
For More Information On This Product,
and
Figure
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
External Bus
9-28.
Slave 2
Acknowledge
Signals
MOTOROLA
Slave 1
9-39