MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 139

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

XER — Integer Exception Register
MSB
3.7.4.3 Condition Register CRn Field — Compare Instruction
3.7.5 Integer Exception Register (XER)
MPC555
USER’S MANUAL
U
0
CRn Bit
CR1 Bit
SO
NOTES:
1. Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
0
1
2
3
When a specified CR field is set by a compare instruction, the bits of the specified field
are interpreted as shown in
by the mfcr, mcrf, and mtcrf instructions.
The integer exception register (XER) is a user-level, 32-bit register.
U
0
1
2
3
1
U
2
1
OV
/
Floating-point exception (FX) — This is a copy of the final state of FPSCR[FX] at the completion of the in-
struction.
Floating-point enabled exception (FEX) — This is a copy of the final state of FPSCR[FEX] at the completion
of the instruction.
Floating-point invalid exception (VX) — This is a copy of the final state of FPSCR[VX] at the completion of
the instruction.
Floating-point overflow exception (OX) — This is a copy of the final state of FPSCR[OX] at the completion
of the instruction.
U
Less than, floating-point less than (LT, FL).
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison).
For floating-point compare instructions, (frA) < (frB).
Greater than, floating-point greater than (GT, FG).
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison).
For floating-point compare instructions, (frA) > (frB).
Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the in-
struction.
For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
3
MPC556
Table 3-9 CRn Field Bit Descriptions for Compare Instructions
U
4
CA
U
5
6
0
Table 3-8 Bit Descriptions for CR1 Field of CR
7
0
8
0
Freescale Semiconductor, Inc.
For More Information On This Product,
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0
0
CENTRAL PROCESSING UNIT
Table
0
Go to: www.freescale.com
0
Rev. 15 October 2000
0
3-9. A condition register field can also be accessed
Reserved
0
RESET:
0
Description
Description
0
0
0
0
0
0
0
0
0
U
U
U
BYTES
MOTOROLA
U
SPR 1
U
U
3-17
LSB
31
U