MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 815

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

D.1 Overview
MPC555 / MPC556
USER’S MANUAL
The following pages provide brief descriptions of the pre-programmed functions in the
TPU3. For detailed descriptions, refer to the programming note for the individual func-
tion. The Motorola
programming notes.
The TPU3 contains four Kbytes of microcode ROM. This appendix defines the func-
tions that are in the standard ROM on the MPC555 / MPC556. The TPU3 can have up
to eight Kbytes of memory and a maximum of four entry tables (see
The TPU3 can address up to eight Kbytes of memory at any one time. It has four
Kbytes of internal ROM, located in Bank 0 and Bank 1, and six Kbytes of dual-ported
SRAM (DPTRAM), located in Bank 0, Bank 1and Bank 2. As only one type of memory
can be used at a time, the TPU3 must either use the internal ROM or the SRAM. Func-
tions from both memory types cannot be used in conjunction.
*The DPTRAM is located at 0x30 2000 until it is switched to emulation mode.
In emulation mode, the DPTRAM is accessible by the TPUs only.
Add - Entry
Add - Entry
Add - Entry
TPUROM
Code
Code
Entry
Code
Code
TPU Literature Pack,
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure D-1 TPU3 Memory Map
TPU ROM FUNCTIONS
7FF
0
1FF
3 FF
Go to: www.freescale.com
TPU ROM FUNCTIONS
Rev. 15 October 2000
APPENDIX D
TPULITPAK/D, provides a list of available
Add - Entry
Add - Entry
DPTRAM*
Code
Entry
Code
Code
1FF
3FF
5 FF
0
Figure
MOTOROLA
D-1).
D-1