MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 667

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.2.2.4 Array Configuration for CMF Module B
19.3 Shadow Information
MPC555
USER’S MANUAL
Programming the shadow information uses the same procedure as programming the
array, except that there are only 256 bytes available in the shadow row. Before starting
the program sequence SIE must equal one.
The SIE bit is write protected by the SES bit for programming operation. Writes will
have no effect if (SES = 1 and PE = 0). The SIE bit can be read whenever the registers
are enabled.
When SIE = 1, normal array accesses are disabled and the shadow information is en-
abled. When an array location is read using supervisor data in this mode, the shadow
information is read from a location determined by the column, 32-byte read page select
and read page word addresses (ADDR[24:29]) of the access. Accessing the CMF con-
trol block registers accesses the registers and not the shadow information. The read
page buffer address monitor is reset whenever SIE is modified, making the next CMF
array access an off-page access.
The default reset state of SIE is normal array access (SIE = 0).
/
MPC556
1. If SIE=1, then the shadow row is enabled instead of the flash block.
Locations 0x4 00000 to 0x4 000F of the shadow row are Reserved by
Motorola for possible future use.
Freescale Semiconductor, Inc.
For More Information On This Product,
32-Kbyte Array Block 5
32-Kbyte Array Block 4
32-Kbyte Array Block 3
32-Kbyte Array Block 2 0x5 0000 – 0x5 7FFF
32-Kbyte Array Block 1
32-Kbyte Array Block 0 and
Shadow Information
CDR MoneT FLASH EEPROM
64-byte Program Page Buffer 5
64-byte Program Page Buffer 4
64-byte Program Page Buffer 3
64-byte Program Page Buffer 2
64-byte Program Page Buffer 1
64-byte Program Page Buffer 0
Go to: www.freescale.com
32-byte Read Page Buffer 1
32-byte Read Page Buffer 0
Rev. 15 October 2000
Bus Interface Unit (BIU)
0x6 8000 – 0x6 FFFF
0x6 0000 – 0x6 7FFF
0x5 8000 – 0x5 FFFF
0x4 8000 – 0x4 FFFF
0x4 0000 – 0x4 7FFF
1
MOTOROLA
19-15