MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 159

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
FETCH
DECODE
READ AND EXECUTE
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
The history buffer maintains the correct architectural machine state. An exception is
taken only when the instruction is ready to be retired from the machine (i.e., after all
previously-issued instructions have already been retired from the machine). When an
exception is taken, all instructions following the excepting instruction are canceled,
i.e., the values of the affected destination registers are restored using the values saved
in the history buffer during the dispatch stage.
Figure 3-4
Table 3-22
fers to the interval from the time an instruction begins execution until it produces a re-
sult that is available for use by a subsequent instruction. Blockage refers to the interval
from the time an instruction begins execution until its execution unit is available for a
subsequent instruction. Note that when the blockage equals the latency, it is not pos-
sible to issue another instruction to the same unit in the same cycle in which the first
instruction is being written back.
2. In the execute stage, each execution unit that has an executable instruction ex-
3. In the writeback stage, the execution unit writes the result to the destination reg-
4. In the retirement stage, the history buffer retires instructions in architectural or-
/
MPC556
ecutes the instruction. (For some instructions, this occurs over multiple cycles.)
ister and reports to the history buffer that the instruction is completed.
der. An instruction retires from the machine if it completes execution with no ex-
ceptions and if all instructions preceding it in the instruction stream have
finished execution with no exceptions. As many as six instructions can be re-
tired in one clock.
shows basic instruction pipeline timing.
indicates the latency and blockage for each type of instruction. Latency re-
Freescale Semiconductor, Inc.
Figure 3-4 Basic Instruction Pipeline
For More Information On This Product,
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Rev. 15 October 2000
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