MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 631

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
1:4
7:8
10
11
12
13
14
15
0
5
6
9
/
MPC556
Name
HOT4
CLKS
BLC
FRZ
CCL
BC
BH
BM
BP
BT
BL
—
Hang on T4
0 = Exit wait on T4 state caused by assertion of HOT4
1 = Enter wait on T4 state
Reserved
Branch latch control
0 = Latch conditions into branch condition register before exiting halted state
1 = Do not latch conditions into branch condition register before exiting the halted state or during
Stop clocks (to TCRs)
0 = Do not stop TCRs
1 = Stop TCRs during the halted state
FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3
FREEZE signal
00 = Ignore freeze
01 = Reserved
10 = Freeze at end of current microcycle
11 = Freeze at next time-slot boundary
Channel conditions latch. CCL controls the latching of channel conditions (MRL and TDL) when
the CHAN register is written.
0 = Only the pin state condition of the new channel is latched as a result of the write CHAN reg-
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write
µPC breakpoint enable
0 = Breakpoint not enabled
1 = Break if µPC equals µPC breakpoint register
Channel breakpoint enable
0 = Breakpoint not enabled
1 = Break if CHAN register equals channel breakpoint register at beginning of state or when
Host service breakpoint enable
0 = Breakpoint not enabled
1 = Break if host service latch is asserted at beginning of state
Link service breakpoint enable
0 = Breakpoint not enabled
1 = Break if link service latch is asserted at beginning of state
MRL breakpoint enable
0 = Breakpoint not enabled
1 = Break if MRL is asserted at beginning of state
TDL breakpoint enable
0 = Breakpoint not enabled
1 = Break if TDL is asserted at beginning of state
the time-slot transition period
ister microinstruction
CHAN register microinstruction
CHAN is changed through microcode
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 17-7 DSCR Bit Descriptions
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
Description
MOTOROLA
17-13