MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 596

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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16.4.4.1 Receive Message Buffer Deactivation
MPC555
USER’S MANUAL
Once these steps are performed, the message buffer functions as an active receive
buffer and participates in the internal matching process, which takes place every time
the TouCAN receives an error-free frame. In this process, all active receive buffers
compare their ID value to the newly received one. If a match is detected, the following
actions occur:
The user should read a received frame from its message buffer in the following order:
If the free running timer is not read, that message buffer remains locked until the read
process starts for another message buffer. Only a single message buffer is locked at
a time. When a received message is read, the only mandatory read operation is that
of the control/status word. This ensures data coherency.
If the BUSY bit is set in the message buffer code, the CPU should defer accessing that
buffer until this bit is negated. Refer to
Because the received identifier field is always stored in the matching receive message
buffer, the contents of the identifier field in a receive message buffer may change if
one or more of the ID bits are masked.
Any write access to the control/status word of a receive message buffer during the pro-
cess of selecting a message buffer for reception immediately deactivates that mes-
sage buffer, removing it from the reception process.
If a receive message buffer is deactivated while a message is being transferred into it,
the transfer is halted and no interrupt is requested. If this occurs, that receive message
buffer may contain mixed data from two different frames.
1. The frame is transferred to the first (lowest entry) matching receive message
2. The value of the free-running timer (captured at the beginning of the identifier
3. The ID field, data field, and RX length field are stored
4. The code field is updated
5. The status flag is set in the IFLAG register
1. Control/status word (mandatory, as it activates the internal lock for this buffer)
2. ID (optional, since it is needed only if a mask was used)
3. Data field word(s)
4. Free-running timer (optional, as it releases the internal lock)
/
MPC556
buffer
field on the CAN bus) is written into the time stamp field in the message buffer
The user should check the status of a message buffer by reading the
status flag in the IFLAG register and not by reading the control/status
word code field for that message buffer. This prevents the buffer from
being locked inadvertently.
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 15 October 2000
Table
NOTE
16-2.
MOTOROLA
16-14

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