MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 79

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

2.3.1.42 VSSSYN
2.3.1.43 ENGCLK/BUCLK
2.3.2 QSMCM PADS
2.3.2.1 PCS[0]/SS/QGPIO[0]
2.3.2.2 PCS[1:3]/QGPIO[1:3]
2.3.2.3 MISO/QGPIO[4]
MPC555
USER’S MANUAL
VDDSYN – This is the power supply of the PLL circuitry.
Pin Name: vsssyn
VSSSYN – This is the power supply of the PLL circuitry.
Pin Name: engclk_buclk
ENGCLK – This is the engineering clock output. Drive strength can be configured to
full strength, half strength or disabled. The drive strength is configured using the EE-
CLK[0:1] bits in the SCCR register in the SIU.
BUCLK – When the chip is in limp mode, it is operating from a less precise on-chip
ring oscillator to allow the system to continue minimum functionality until the system
clock is fixed. This backup clock can be seen externally based on the values of the EE-
CLK[0:1] bits in the SCCR register in the USIU.
Pin Name: pcs0_ss_b_qgpio0
PCS[0] – This signal provides QSPI peripheral chip select 0.
SS – Assertion of this bi-directional signal places the QSPI in slave mode.
QSPI GPIO[0] – When this pin is not needed for a QSPI application it can be config-
ured as a general purpose input/output.
Pin Name: pcs1_qgpio1 - pcs3_qgpio3 (3 pins)
PCS[1:3] – These signals provide three QSPI peripheral chip selects.
QGPIO[1:3] – When these pins are not needed for QSPI applications they can be con-
figured as a general purpose input/output.
Pin Name: miso_qgpio4
Master-In Slave-Out (MISO) – This bi-directional signal furnishes serial data input to
the QSPI in master mode, and serial data output from the QSPI in slave mode.
QGPIO[4] – When this pin is not needed for a QSPI application it can be configured
as a general purpose input/output.
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MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
MOTOROLA
2-21