MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 403

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.1 Features
1.
MPC555 / MPC556
USER’S MANUAL
The user should not perform instruction fetches from modules on the IMB.
The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the
CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus com-
munication between the U-bus and the IMB3.
The UIMB interface consists of seven submodules that control bus interface timing,
address decode, data multiplexing, intrasystem communication (interrupts), and clock
generation to allow communication between U-bus and the IMB3. The seven submod-
ules are:
• U-bus interface
• IMB3 interface
• Address decoder
• Data multiplexer
• Interrupt synchronizer
• Clock control
• Scan control
• Provides complete interfacing between the U-bus and the IMB3:
• Support of 32-bit and 16-bit BIUs for IMB3 modules
• Half and full speed operation of IMB3 bus with respect to U-bus
• Simple “slave only” U-bus interface implementation
• Supports scan control for modules on the IMB3 and on the U-bus
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface
— Burst-inhibited accesses to the modules on IMB3
— Supports alternate master on IMB3
— Transparent mode operation not supported
— Relinquish and retry not supported
address range
Modules on the IMB3 bus can only be reset by SRESET. Some mod-
ules may have a module reset, also.
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Freescale Semiconductor, Inc.
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Go to: www.freescale.com
Rev. 15 October 2000
SECTION 12
NOTE
1
MOTOROLA
12-1