MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 301

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Burst data in progress
Special transfer start
Cancel reservation
Kill reservation
Signal Name
Transfer start
/
RETRY
MPC556
BDIP
STS
CR
KR
TS
Table 9-1 MPC555 / MPC556 SIU Signals (Continued)
Freescale Semiconductor, Inc.
Pins
1
1
1
1
1
1
For More Information On This Product,
EXTERNAL BUS INTERFACE
Active
Go to: www.freescale.com
Low
Low
Low
Low
Low
Low
Rev. 15 October 2000
Reservation Protocol
Transfer Start
I/O
O
O
O
O
I
I
I
I
I
In the case of regular transaction, this signal is driven
by the slave device to indicate that the MPC555 /
MPC556 must relinquish the ownership of the bus and
retry the cycle.
When an external master owns the bus and the inter-
nal MPC555 / MPC556 bus initiates access to the ex-
ternal bus at the same time, this signal is used to
cause the external master to relinquish the bus for one
clock to solve the contention.
Driven by the MPC555 / MPC556 when it owns the
external bus. It is part of the burst protocol. When
BDIP is asserted, the second beat in front of the cur-
rent one is requested by the master. This signal is ne-
gated prior to the end of a burst to terminate the burst
data phase early.
Driven by an external master when it owns the exter-
nal bus. When BDIP is asserted, the second beat in
front of the current one is requested by the master.
This signal is negated prior to the end of a burst to ter-
minate the burst data phase early. The MPC555 /
MPC556 does not support burst accesses to internal
slaves.
Driven by the MPC555 / MPC556 when it owns the
external bus. Indicates the start of a transaction on the
external bus.
Driven by an external master when it owns the exter-
nal bus. It indicates the start of a transaction on the
external bus or (in show cycle mode) signals the be-
ginning of an internal transaction.
Driven by the MPC555 / MPC556 when it owns the
external bus. Indicates the start of a transaction on the
external bus or signals the beginning of an internal
transaction in show cycle mode.
Each PowerPC CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX instruc-
tion issued by the RCPU to a non-local bus on which
the
nal is used by the non-local bus interface to backoff
the cycle. Refer to
tails.
storage reservation
9.5.9 Storage Reservation
Description
has been lost, this sig-
MOTOROLA
for de-
9-5