R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1005

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.87 Overflow Alert FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the E-MAC. The
threshold can be set by the size of the receive FIFO data (bits RFD[7:0]) and the number of
receive frames (bits RFF[4:0]).
If the same receive FIFO size as set by the FIFO depth register (FDR) is set when flow control is
turned on according to the RFD setting condition, flow control is turned on with (FIFO data size −
64) bytes. For instance, when the RFD bits in FDR = 7 and the RFD bits in this register = 7, flow
control is turned on when (2,048 − 64) bytes of data is stored in the receive FIFO. The value set in
the RFD bits in this register should be equal to or less than that set in the RFD bits in FDR.
Flow control is turned on when either of the setting conditions of bits RFF[4:0] and bits RFD[7:0]
is satisfied. Flow control is turned off when neither of the conditions is satisfied (release).
Bit
31 to 21
20 to 16
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

RFF[4:0]
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
H'17
28
12


R
R
0
0
27
11


R
R
0
0
R/W
R
R/W
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive FIFO Overflow Alert Signal Output Threshold
H'00: When one receive frame has been stored in the
H'01: When two receive frames have been stored in the
H'16: When 23 receive frames have been stored in the
H'17: When 24 receive frames have been stored in the
25

R

R
0
9
0
:
receive FIFO
receive FIFO
receive FIFO
receive FIFO
24

R

R
0
8
0
:
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
23

R
0
7
1
Rev. 2.00 May 22, 2009 Page 935 of 1982
R/W
22

R
0
6
1
R/W
21

R
0
5
1
R/W
R/W
20
1
4
1
RFD[7:0]
R/W
R/W
19
0
3
1
RFF[4:0]
REJ09B0256-0200
R/W
R/W
18
1
2
1
R/W
17
1
1
1
R/W
R/W
16
1
0
1