R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1684

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 37 LCD Controller (LCDC)
Rev. 2.00 May 22, 2009 Page 1614 of 1982
REJ09B0256-0200
Bit
12
11
10
Bit Name
VEINTEN
MINTS
FINTS
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at
the end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
1: Interrupt at the end point of the Vsync signal is
Memory Access Interrupt State
Indicates the memory access interrupt handling
state.
This bit indicates 1 when the LCDC memory access
interrupt is generated (set state). During the
memory access interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a memory access
1: LCDC has generated a memory access end
Flame End Interrupt State
Indicates the flame end interrupt handling state.
This bit indicates 1 at the time when the LCDC
flame end interrupt is generated (set state). During
the flame end interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a flame end interrupt or
1: LCDC has generated a flame end interrupt and
interrupt or has been informed that the generated
memory access interrupt has completed
interrupt and not yet been informed that the
generated memory access interrupt has
completed
has been informed that the generated flame end
interrupt has completed
not yet been informed that the generated flame
end interrupt has completed
disabled
enabled

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