R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1126

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 26 I
26.5
26.5.1
In order to set up the master interface to transmit a data packet on the I
procedure:
(1)
1. SCL clock generation divider (SCGD) = H'03
2. Clock division ratio (CDF) = H'3
(2)
1. Master address register = address of slave being accessed and STM1 bit (write mode: 0)
2. Transmit data register = first data byte to be transmitted
3. Master control register = H'89
(3)
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).
2. Set the master control register to H'88 (To suspend the data transmission, the master device
3. Reset the MAT bit.
(4)
1. Wait for master event, MDE in the master status register.
2. Transmit data register = subsequent data.
Rev. 2.00 May 22, 2009 Page 1056 of 1982
REJ09B0256-0200
(SCL frequency of 400 kHz)
(The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(MDBS = 1, MIE = 1, ESG = 1)
will hold the SCL low until the MDE bit is cleared.)
If only one byte of data is transmitted, set the master control register to H'8A, meaning that the
stop generation is enabled. This generates a stop on the bus as soon as one byte has been
transmitted.
Load Clock Control Register
Load Master Control Register (First Data Byte and Address)
Wait for Outputting Address
Monitor Transmission of Data
Programming Examples
Master Transmitter
2
C Bus Interface (IIC)
2
C bus, follow the following

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