R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 656

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.8
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status. DMAOR is a common register for
channel 0 to 5.
Rev. 2.00 May 22, 2009 Page 586 of 1982
REJ09B0256-0200
Initial value:
Bit
15, 14
13, 12
11, 10
R/W:
Bit:
DMA Operation Register (DMAOR)
Bit Name
—
CMS[1:0]
—
15
R
0
14
R
0
R/W
13
CMS[1:0]
Initial
Value
All 0
00
0
All 0
R/W
12
0
R/W
R
R/W
R
11
R
0
10
R
0
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select
Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channel bus modes are set to
cycle steal mode to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
9
PR[1:0]
0
Executes one DMA transfer in each of 16 clocks of
an external bus clock.
Executes one DMA transfer in each of 64 clocks of
an external bus clock.
R/W
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R/(W)*R/(W)* R/W
AE
2
0
NMIF DME
1
0
0
0