R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1019

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
31
30
Bit
Name
RACT
RDLE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Descriptor Valid/Invalid
Indicates whether this descriptor is valid or invalid. To make
this bit valid, prepare a receive buffer (user-specified
receive data storage destination) beforehand, then write 1
to this bit. The E-DMAC clears this bit to 0 after data
transfer.
0: Indicates that this receive descriptor is invalid
1: Indicates that this receive descriptor is valid
Receive Descriptor List End
Indicates whether this descriptor is the last descriptor of the
descriptor row (descriptor list).
0: Not last descriptor
1: Last descriptor
After transfer of this descriptor, the E-DMAC reads the
Indicates the initial setting state, the state after 0 is
If this state is recognized when the E-DMAC reads a
written to, or (in case the user writes 1 to this bit) that this
bit is cleared to 0 because the E-DMAC data transfer
processing is completed
descriptor, the E-DMAC clears the RR bit in EDRRR to
0, and halts transfer operation related to reception by the
E-DMAC
Indicates that data is not transferred yet after the user
writes 1 to this bit, or that data is being transferred
When there is a descriptor row (descriptor list) consisting
of multiple continuous descriptors, the E-DMAC can
continue operation when this bit of the next descriptor is
valid
After transfer of this descriptor, the E-DMAC reads the
next one in the list of continuous descriptors
descriptor placed at the address indicated by RDLAR
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 949 of 1982
REJ09B0256-0200