R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 2043

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Interrupt controller (INTC)..................... 233
Interrupt response time ........................... 308
IP Security Accelerator (SECURITY).... 997
IRL interrupts ......................................... 293
IRQ interrupts ......................................... 292
Issue rates ................................................. 94
ITLB ....................................................... 159
ITLB address array ................................. 173
ITLB data array ...................................... 174
L
L memory ............................................... 217
LCD controller (LCDC) ....................... 1587
LCD module power-supply states......... 1639
List processor........................................ 1493
Little endian.............................................. 52
Load-store architecture ............................. 57
Local bus state controller (LBSC) .......... 319
Logic operation instructions ..................... 70
M
Magic packet detection ........................... 983
Manual PAUSE frame transmission ....... 982
Manual reset ........................................... 116
Master Mode........................................... 408
Master Mode 1...................................... 1228
Memory management unit.............. 137, 324
Memory-mapped registers ........................ 51
MII frame................................................ 986
MII registers ................................... 991, 992
MII-RMII conversion circuit .................. 993
MMC Mode .......................................... 1328
Module standby mode............................. 682
Multi-Buffer frame ................................. 973
Multimedia card interface (MMCIF) .... 1287
Multiple interrupts .................................. 307
Multiple virtual memory mode ............... 145
N
NMI (nonmaskable interrupt) ................. 132
NMI interrupt.......................................... 292
Notes on display-off mode
(LCDC stopped).................................... 1640
O
On-chip module interrupts ...................... 295
On-chip peripheral module request
mode ....................................................... 594
One-shot operation.................................. 757
Operand access cycle break .................. 1787
P
P0, P3, and U0 areas ............................... 142
P1 area..................................................... 142
P2 area..................................................... 142
P4 area..................................................... 142
Padding insertion .................................... 975
Page size bits........................................... 157
PAUSE frame reception.......................... 983
PC card controller (PCC) ...................... 1361
PCI Controller (PCIC) ............................ 451
Phase counting mode .............................. 742
PHY-LSI ................................................. 986
Pipelining .................................................. 79
Power-Down mode ......................... 436, 669
Power-down state...................................... 53
Power-on reset ........................................ 116
Power-supply control sequences ........... 1635
PPN ......................................................... 157
Pre-execution user break/
post-execution user break........................ 130
Prefetch instruction ................................. 229
PRI .......................................................... 783
Privileged mode ........................................ 38
Processing modes...................................... 38
Rev. 2.00 May 22, 2009 Page 1973 of 1982
REJ09B0256-0200