R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 751

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.5
18.5.1
Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the
program execution state to software standby mode. In software standby mode, not only the CPU
but also the clock and on-chip peripheral modules halt. However, the clock output from the
CLKOUT pin continues when the CKOEN bit in the PLLCR register of the CPG is set to 1. When
the CKOEN bit is 0, a low level is output from the CLKOUT pin.
The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip
peripheral modules are initialized.
The procedure for a transition to software standby mode is as follows:
1. Set the STBY bit in STBCR to 1.
2. Execute the SLEEP instruction.
3. Software standby mode is entered and the clocks within the LSI are halted. The output on the
All modules should be stopped before the above procedure is executed.
18.5.2
Software standby mode is canceled by an interrupt (NMI or IRQ/IRL) or a reset.
(1)
When an NMI or IRQ, occurs, software standby mode is canceled and the STATUS0 pin goes
low. Thereafter, interrupt exception handling is executed and a code indicating the interrupt source
is set in INTEVT. After branching to the interrupt service routine, clear the STBY bit in the
STBCR register back to 0. Since interrupts are accepted in software standby mode even when the
BL bit in SR is 1, save SPC and SSR to the stack before executing the SLEEP instruction if
necessary.
Immediately after an interrupt is detected, the clock output on the CLKOUT pin may be unstable
until software standby mode is canceled.
STATUS0 pin goes high.
Canceling with Interrupt
Software Standby Mode
Transition to Software Standby Mode
Canceling Software Standby Mode
Rev. 2.00 May 22, 2009 Page 681 of 1982
Section 18 Power-Down Mode
REJ09B0256-0200