R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1245

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(6)
Figure 28.19 shows a sample flowchart for simultaneous serial data transmission and reception.
Use the following procedure for simultaneous serial transmission and reception after enabling the
SCIF for both transmission and reception.
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 28.19 Sample Simultaneous Serial Transmission and Reception Flowchart
No
No
No
Start of transmission and reception
End of transmission and reception
Write transmit data to SCFTDR,
Read ORER flag in SCLSR
Read TDFE flag in SCFSR
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Clear TE and RE bits
Read receive data in
and clear TDFE flag
flag in SCFSR to 0
All data received?
in SCFSR to 0
in SCSCR to 0
Initialization
ORER = 1?
TDFE = 1?
RDF = 1?
Yes
No
Yes
Yes
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Error handling
[4]
[5]
[1]
[2]
Yes
[3]
Note:
[1] SCIF initialization:
[2] SCIF status check and transmit data write:
[3] Receive error handling:
[4] SCIF status check and receive data read:
[5] Serial transmission and reception continuation procedure:
Read SCFSR and check that the TDFE flag is set to 1,
then write transmit data to SCFTDR, and clear the
TDFE flag to 0. The transition of the TDFE flag from 0
to 1 can also be identified by a TXI interrupt.
See Sample SCIF Initialization Flowchart in figure
28.13.
Read the ORER flag in SCLSR to identify any error,
perform the appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be resumed while the
ORER flag is set to 1.
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from 0 to 1 can also
be identified by an RXI interrupt.
To continue serial transmission and reception, read 1
from the RDF flag and the receive data in SCFRDR,
and clear the RDF flag to 0 before receiving the MSB
in the current frame. Similarly, read 1 from the TDFE
flag to confirm that writing is possible before transmitting
the MSB in the current frame. Then write data to
SCFTDR and clear the TDFE flag to 0.
When switching from a transmit operation or receive
operation to simultaneous transmission and reception
operations, clear the TE and RE bits to 0, and then
set them simultaneously to 1.
Rev. 2.00 May 22, 2009 Page 1175 of 1982
REJ09B0256-0200