R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 730

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Watchdog Timer and Reset (WDT)
WDTBCNT is an 18-bit up-counter operated on the peripheral clock0 (Pck0). WDTBCNT is
cleared when H'55 is set to the bits 31 to 24 in WDTBST.
If the peripheral clock frequency is 66.6 MHz, the WDTBCNT overflow time is approximately
×
3.932 ms (= 2^18 [bit]
1/66.6 [MHz]).
WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The
time until WDTCNT overflows becomes the maximum value when H'000 is set to WDTST.
Where the peripheral clock frequency is 66.6 MHz, the maximum overflow time is approximately
×
16.105 s (= 2^12 [bit]
3.932 [ms]).
And the time until WDTCNT overflows becomes the minimum value when H'5A000001 is set to
×
WDTST. The minimum overflow time is approximately 3.932 ms (= 2^1 [bit]
3.932 [ms]).
17.4.5
Clearing WDT Counter
Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow
setting value to WDTST clears WDTCNT.
Rev. 2.00 May 22, 2009 Page 660 of 1982
REJ09B0256-0200