R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 622

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
The PCIC detects when the power state (PS) bit of the PCI power management control/status
register changes (when it is written to from an external PCI device), and issues a power
management interrupt. To control the power management interrupts, there are the PCI power
management interrupt register (PCIPINT) and PCI power management interrupt mask register
(PCIPINTM). Of the power management interrupts, the power state D0 interrupt (PCIPWD0)
detects a transition from the power state D1/D2/D3 to D0, while power state D1 interrupt
(PCIPWD1) detects a transition from the power state D0 to D1, while power state D2 interrupt
(PCIPWD2) detects a transition from the power state D0/D1 to D2, while power state D3 interrupt
(PCIPWD3) detects a transition from the power state D0/D1/D2 to D3. Interrupt masks can be set
for each interrupt.
No power state D0 interrupt is generated at a power-on reset.
The following cautions should be noted when the PCIC is operating in normal mode and a power
down interrupt is received from the host: In PCI power management, the PCI local bus clock stops
within a minimum of 16 clocks after the host device has instructed a transition to power state D3.
After detecting a power state D3 interrupt, do not, therefore, attempt to read or write to local
registers and configuration registers that can be accessed from the SuperHyway bus and PCI local
bus access (I/O and memory spaces). Because these accesses operate using the PCI local bus
clock, the cycle for these accesses will not be completed if the clock stops and may be hung-up on
the SuperHyway bus.
13.4.8
The PCIC of this LSI conforms to the PCI local bus specification revision 2.2 stipulations and can
be connected to a device with a PCI local bus interface. The following figures show the timing for
each operation mode.
Rev. 2.00 May 22, 2009 Page 552 of 1982
REJ09B0256-0200
PCI Local Bus Basic Interface
Figure 13.16 PCI Local Bus Power Down State Transition
(bus idle)
(normal)
D0
D1
(power down)
(clock stop)
D2
D3