R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 435

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Local Bus State Controller (LBSC)
While the PCMCIA interface is used, the CE1A/CS5 and CE2A signals, the RD signal, (which
can be used as OE), the WE0, WE1, WE2, and WE3 signals, (which can be used as, PCC_REG,
WE, IORD, and IOWR, respectively) are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS5WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS5 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS5WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
For the PCMCIA interface, the setup time of addresses to the read/write strobe signals (CE1A/CS5
and CE2A) can be specified within a range from 0 to 15 cycles through bits TEDA[2:0],
TEDB[2:0], TEHA[2:0], and TEHB[2:0] in CS5PCR. In addition, the number of wait cycles can
be specified within a range from 0 to 50 cycles through bits PCWA[1:0] and PCWB[1:0] The
number of wait cycles specified by CS5PCR is added to the value specified by IW[3:0] in
CS5WCR or PCIW[3:0] in CS5PCR.
When the DDR-SDRAM is used, see section 12, DDR-SDRAM Interface (DDRIF).
(7)
Area 6
For area 6, external address bits A28 to A26 are 110.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM, and PCMCIA
interfaces.
When the SRAM or burst ROM is used, a bus width of 8, 16, or 32 bits is selectable with bits
SZ[1:0] in CS6BCR. When the MPX interface is used, a bus width of 32 bits should be selected
through bits SZ[1:0] in CS6BCR. When the PCMCIA interface is used, select a bus width of 8 or
16 bits with SZ[1:0] in CS6BCR. For details, see section 11.3.2, Memory Bus Width.
While the SRAM interface is used, the CS6 signal is asserted when area 6 is accessed. In addition,
the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
While the PCMCIA interface is used, the CE1B/CS6 and CE2B signals, the RD signal (which can
be used as OE), and the WE0, WE1, WE2, and WE3 signals (which can be used as PCC_REG,
WE, IORD, and IOWR, respectively) are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS6WCR can be selected.
Rev. 2.00 May 22, 2009 Page 365 of 1982
REJ09B0256-0200